1. Field of the Invention
The present invention generally relates to an ASIC element including an active front side, in which circuit functions are implemented, and including at least one via, which establishes an electrical connection between the active front side and the rear side of the element.
2. Description of the Related Art
Of particular significance is the use of ASIC elements including vias in the context of vertically integrated hybrid components. Such components generally include multiple different elements, which are installed one above the other in the form of a chip stack. Advantageously, the different functionalities of the elements of a component usually complement one another to achieve an application. The electrical connection between the individual elements of a vertically integrated hybrid component and also its external contacting are frequently achieved with the aid of vias, which is advantageous both for reasons of miniaturization and in the 2nd level assembly. The elements, which are combined in a vertically integrated hybrid component, may be MEMS elements having a micromechanical functionality as well as ASIC elements having a purely circuitry-wise functionality. In connection with vertically integrated hybrid components, ASIC elements are also used frequently for capping the micromechanical structure of an MEMS element. For example, vertically integrated hybrid inertial sensor components including a micromechanical sensor element and an ASIC element are known, into which the evaluation circuit for the sensor signals is integrated. In these inertial sensor components, the ASIC element is installed above the sensor structure of the MEMS element and seals it against environmental influences.
A number of implementation concepts for vias in ASIC elements are known from the related art, which are also suitable for the design of vertically integrated hybrid components and in particular for the so-called wafer-level packaging, in which the individual elements are installed in the wafer composite and only later separated as a package.
According to a known approach, the via is created in connection with the processing of the ASIC substrate, specifically as a blind opening in the ASIC substrate. This blind opening is then completely filled with a metal, such as copper or tungsten, or with a metallic layer and a dielectric, so that the surface of the ASIC substrate is preferably sealed and is flat for further processing. The rear side of this form of via is exposed and contacted only after the ASIC substrate is installed on another substrate, for example, by thinning the rear side of the ASIC substrate. In this form of implementation, the metallic core or the metallic printed conductor track of the via is protected against external influences by completely filling the blind opening or via.
Since such vias generally have a large aspect ratio, both the structuring method for producing the corresponding opening in the ASIC substrate as well as the filling are comparatively complex.